A one-shot timer circuit

A one-shot timer circuit or interval timer when input trigger pulse
applied. Out put will change to high and remain high until end of
delay time out put will change to low

This circuit used LM555 in monostable operation
The external capacitor is initially held discharged
by a transistor inside the timer. Upon application of a negative
trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is
set which both releases the short circuit across the capacitor
and drives the output high.

During the timing cycle when the output is high, the further
application of a trigger pulse will not effect the circuit so long
as the trigger input is returned high at least 10μs before the
end of the timing interval. However the circuit can be reset
during this time by the application of a negative pulse to the
reset terminal (pin 4). The output will then remain in the low
state until a trigger pulse is again applied.

Figure below is a nomograph for easy determination of R, C
Values for various time delays of lm555 timer